NDLI: Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input

Content Provider	IEEE Xplore Digital Library
Author	Fayomi, C.J.B. Roberts, G.W. Sawan, M.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada (Fayomi, C.J.B.)
Abstract	A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.
Starting Page	653
Ending Page	656
File Size	443275
Page Count	4
File Format	PDF
ISBN	0780354826
DOI	10.1109/ISCAS.2000.857549
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-28
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low voltage Latches Delay Rail to rail operation Transconductance Operational amplifiers Rail to rail amplifiers Circuit simulation CMOS digital integrated circuits CMOS process
Content Type	Text
Resource Type	Article

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