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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tang, K.T. Friedman, E.G. |
| Copyright Year | 2000 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA (Tang, K.T.) |
| Abstract | Expressions characterizing the output voltage and propagation delay of a CMOS inverter driving a resistive-capacitive interconnect are presented in this paper. The MOS transistors are characterized by the nth power law model. In order to emphasize the nonlinear behavior of a CMOS inverter, the interconnect is modeled as a lumped RC load. The propagation delay of a CMOS inverter is characterized for both a fast ramp and a slow ramp input signal. The waveform of the output voltage based on these analytic equations is quite close to SPICE assuming a fast ramp input signal. The accuracy of the propagation delay model for both fast ramp and slow ramp input signals is within 7% as compared to SPICE simulations. |
| Starting Page | 269 |
| Ending Page | 272 |
| File Size | 425472 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780354826 |
| DOI | 10.1109/ISCAS.2000.858740 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-05-28 |
| Publisher Place | Switzerland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Transient analysis Inverters Integrated circuit interconnections Semiconductor device modeling Propagation delay MOSFETs Voltage Impedance Signal analysis Equations |
| Content Type | Text |
| Resource Type | Article |
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