NDLI: Low power full-search block-matching motion estimation chip for H.263+

Content Provider	IEEE Xplore Digital Library
Author	Jun-Fu Shen Liang-Gee Chen Hao-Chieh Chang Tu-Chih Wang
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Jun-Fu Shen)
Abstract	In this paper, a low power full-search block matching (FSBM) motion estimation design for the H.263+ low bit rate video coding was proposed. The features of H.263+ such as half-pixel precision and some advanced modes (advance prediction mode, PB-frame mode and reduced resolution update mode) are taken into consideration. This architecture can deal with different block size and searching range in a single chip without any latency. We use a 1-D and 2-D mixed architecture to fulfill this goal. To achieve the purpose of low power and reduce the design period, we use dual supply voltage levels in this chip. This chip is realized by TSMC 0.6 /spl mu/m single-poly triple-metal CMOS technology. The operation frequency is set at 60 MHz to meet the requirement of the real time processing in the reduced resolution update mode in H.263+. The power consumption is 424 mW at 60 MHz and the throughput is 36 frames per second with CIF format at 60 MHz.
Starting Page	299
Ending Page	302
File Size	421302
Page Count	4
File Format	PDF
ISBN	0780354710
DOI	10.1109/ISCAS.1999.780001
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Motion estimation Computer architecture Bit rate CMOS technology Energy consumption Bandwidth Shift registers Video coding Delay Voltage
Content Type	Text
Resource Type	Article

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