NDLI: Analytical expressions for average bit statistics of signal lines in DSP architectures

Content Provider	IEEE Xplore Digital Library
Author	Bobba, S. Hajj, I.N. Shanbhag, N.R.
Copyright Year	1998
Description	Author affiliation: Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA (Bobba, S.)
Abstract	Accurate high-level power estimation methods are required for exploring the design space to obtain an, optimal low-power circuit. DSP architectures are regular and they consist of interconnected macro-blocks such as adders and multipliers. Previously the power dissipation of macro-blocks was related to the average bit statistics. Given the input word-level statistics for a DSP architecture, the word-level statistics at all the internal signal lines can be computed analytically using transfer function evaluation or by propagating the statistics. In this paper, we present simple analytical expressions for computing the average bit statistics using the word-level statistics of the signal lines in a DSP architecture.
Starting Page	33
Ending Page	36
File Size	424632
Page Count	4
File Format	PDF
ISBN	0780344553
DOI	10.1109/ISCAS.1998.705205
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal analysis Statistical analysis Digital signal processing Computer architecture Space exploration Integrated circuit interconnections Adders Power dissipation Statistics Transfer functions
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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