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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Stevens, K.S. Suter, B.W. |
| Copyright Year | 1998 |
| Description | Author affiliation: Strategic CAD Labs., Intel Corp., Portland, OR, USA (Stevens, K.S.) |
| Abstract | Architecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations have been applied to create a power efficient architecture of an FFT. This architecture has been implemented in asynchronous circuit technology that achieves significant power reduction over other FFT architectures. Multirate signal processing concepts are applied to the FFT to localize communication and remove the need for globally shared results in the FFT computation. A novel architecture is produced from the polyphase components that is mapped to an asynchronous implementation. The asynchronous design continues the localization of communication and can be designed using standard cell libraries such as radiation-tolerant libraries for space electronics. We present a methodology based on multirate signal processing techniques and asynchronous design style that supports significant reduction in power over conventional design practices. A test chip implementing part of this design has been fabricated and power comparisons have been made. |
| Starting Page | 21 |
| Ending Page | 24 |
| File Size | 400274 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780344553 |
| DOI | 10.1109/ISCAS.1998.706798 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-05-31 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer architecture Signal processing Libraries Signal design Circuit synthesis Very large scale integration Asynchronous circuits CMOS technology Communication standards Testing |
| Content Type | Text |
| Resource Type | Article |
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