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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jiann-Horng Tsay Shen-Iuan Liu Yan-Pei Wu |
| Copyright Year | 1996 |
| Description | Author affiliation: Dept. of Electron. Eng., Lunghwa Junior Coll. of Technol. & Commerce, Taoyuan, Taiwan (Jiann-Horng Tsay) |
| Abstract | By using a MOS active attenuator which contains only two MOS transistors fabricated in a common substrate, a technique is presented to extract the threshold voltage of a MOSFET under tests. The active attenuator can be easily implemented with very small chip area in the test chips of a wafer and the extracting procedure can be performed quite fast. Hence, this technique is suitable for threshold voltage extraction that is important in MOSFET characterization and process monitoring. HSPICE Simulation and experimental results are given to verify this proposed scheme. |
| Starting Page | 397 |
| Ending Page | 400 |
| File Size | 355505 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780330730 |
| DOI | 10.1109/ISCAS.1996.539968 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-05-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Attenuation measurement Voltage measurement Threshold voltage MOSFET circuits Attenuators Testing Semiconductor device measurement Educational institutions Business Performance evaluation |
| Content Type | Text |
| Resource Type | Article |
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