NDLI: Design of a 3 V-50 MHz analog CMOS current-mode NRL filter

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FM signal generation using delta-sigma oscillators

A minimal multibit digital noise shaping architecture

An efficient design method for the modulator of high-order /spl Sigma//spl Delta/ ADCs

A new multistage bandpass sigma-delta modulator

A general approach to the AC and DC analysis of a class of sigma-delta modulator configurations

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Trimming of current mode DACs by adjusting V/sub t/

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VCO with double cross-coupled high-speed and low-power multivibrator architecture

An exponential-law element with temperature compensation

Linear transfer function synthesis using non-linear IC components

Comparison of dithering and adaptive schemes used in sigma-delta modulators

A novel clock feed-through distortion cancellation method for SI-circuits

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A capacitor-area efficient realization of sigma-delta modulator-based FIR/IIR analog linear-phase filters

On the design of high-speed high-resolution track and holds

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MOSFET-C filter design based on impedances simulation

Automatic tuning system for high-frequency integrated continuous-time filters

Tunable capacitors for digital CMOS compatible high frequency analog filters

Efficient tunable continuous-time integrated current-mode filter designs

A fuzzy logic system for analog fault diagnosis

Worst-case parameters derived from device physics

Rank-order filtering in analog VLSI

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Design of a 3 V-50 MHz analog CMOS current-mode NRL filter

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The effects of mismatch in complex bandpass /spl Delta//spl Sigma/ modulators

An analysis of dynamic element matching techniques in sigma-delta modulation

Multi-bit DAC with noise-shaped element mismatch

The matching of small capacitors for analog VLSI

/spl plusmn/0.75 V BiCMOS four quadrant analog multiplier with rail-rail input signal-swing

A new filter building block in CMOS technology

A buffered, constant gain, opamp with rail-to-rail common-mode range

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Novel electronically tunable current-mode filter without external passive elements

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Pulse based signal processing: VLSI implementation of a Palmo filter

New dual output transconductance amplifier based biquad

An area efficient low noise 100 Hz low-pass filter

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An analog memory for a QCIF format image frame storage

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Issues in the synthesis of voltage-, current-, and voltage-current-mode circuits

A simple universal LV/LP opamp architecture

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Design of a 3 V-50 MHz analog CMOS current-mode NRL filter

Content Provider	IEEE Xplore Digital Library
Author	Jai-Sop Hyun Yoon, K.S.
Copyright Year	1996
Description	Author affiliation: Dept. of Electron. Eng., INHA Univ., Incheon, South Korea (Jai-Sop Hyun; Yoon, K.S.)
Abstract	A 3 voltage analog CMOS current-mode continuous-time filter with a negative resistance load (NRL) is proposed. To design a current integrator, a modified basic current mirror with an NRL to increase the output resistance is employed The current integrator is designed to enhance the frequency behavior and operate in low voltage by employing a basic current mirror structure and diode connected input transistor. The third order Butterworth low pass active filter using a current-mode NRL integrator is synthesized and simulated for a 1.5 /spl mu/m CMOS n-well standard process. Simulation results illustrate the cutoff frequency of 50 MHz and power consumption of 2.4 mW/pole with a 3 V power supply. The chip layout area of the third order low pass active filter only occupies 1 mm/sup 2/.
Starting Page	129
Ending Page	132
File Size	310337
Page Count	4
File Format	PDF
ISBN	0780330730
DOI	10.1109/ISCAS.1996.539825
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-05-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mirrors Circuits Voltage Active filters Power supplies Bandwidth Frequency MOSFETs Signal processing Transconductance
Content Type	Text
Resource Type	Article

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