NDLI: Optimal manufacturable CNN array size for time multiplexing schemes

Content Provider	IEEE Xplore Digital Library
Author	Gunhee Han Pineda de Gyvez, J. Sanchez-Sinencio, E.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA (Gunhee Han)
Abstract	This paper presents a feasibility analysis to predict the optimal size of VLSI CNN implementations. A 3/spl times/3 CNN IC test prototype was designed and fabricated for this purpose. The study considers both the manufacturability and computing performance power of hypothetical large CNN arrays. The manufacturability analysis has been geared towards IC yield prediction using our actual IC layout along with some realistic parameters representing the "cleanliness" of the manufacturing line. Additionally, from experimental results we have found that offset effects are dominant and if they are not properly canceled they can produce incorrect processing results. As a one-on-one mapping between image pixels and CNN cells is practically impossible, the computing performance analysis concentrates on the optimal array size needed to efficiently implement a multiplexing scheme versus the hypothetical fully parallel CNN architecture. Our results indicate that a 50/spl times/50 array is feasible for a time multiplexing scheme. This array will consume around 4 W. The predicted yield of such array is about 70%. The implementation cost is around 30% of a 100/spl times/100 array, or alternatively only 2% of a 200/spl times/200 array, and only 0.04% slower than a hypothetical fully parallel processing architecture.
Starting Page	387
Ending Page	392
File Size	415642
Page Count	6
File Format	PDF
ISBN	078033261X
DOI	10.1109/CNNA.1996.566605
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-06-24
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cellular neural networks Integrated circuit layout Very large scale integration Integrated circuit testing Prototypes Computer aided manufacturing Pixel Concurrent computing Performance analysis Computer architecture
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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