NDLI: Hardware implementation of CNN

Content Provider	IEEE Xplore Digital Library
Author	Veni, S. Yamuna, B.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Amrita Vishwa Vidyapeetham, Coimbatore, India (Veni, S.; Yamuna, B.)
Abstract	The requisite properties of analog CNN components, like the Gilbert multiplier, Operational transconductance amplifier, and the current mirror, were separately estimated. Interconnect for a single cell was analyzed , and extended for a 3 /spl times/3 CNN, that has been implemented. A programmable integration time-constant and a template programmability is found possible. It is also seen that implementation is possible at very low power levels, typically 124 uW. The network considered in this design is a continuous-time rectangular type CNN with r = 1. In this paper the network was implemented using analog VLSI techniques and their performance was verified using cadence spectre IC5. The designed CNN could be used for the applications such as image processing, solution of partial differential equation, modelling of nonlinear phenomenon, physical system simulation, etc.
Sponsorship	Univ. of Melbourne Faculty of Eng
Starting Page	320
Ending Page	325
File Size	1022568
Page Count	6
File Format	PDF
ISBN	0780388402
DOI	10.1109/ICISIP.2005.1529469
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image processing Integrated circuit interconnections Computer architecture Very large scale integration Analog computers Analog circuits Parallel processing Hardware Cellular neural networks Voltage control
Content Type	Text
Resource Type	Article

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