NDLI: TCAD modeling of accumulated damage during time-dependent mixed-mode stress

Content Provider	IEEE Xplore Digital Library
Author	Raghunathan, U.S. Chakraborty, P.S. Wier, B. Cressler, J.D. Yasuda, H. Menz, P.
Copyright Year	2013
Description	Author affiliation: Sch. of ECE, Georgia Tech, Atlanta, GA, USA (Raghunathan, U.S.; Chakraborty, P.S.; Wier, B.; Cressler, J.D.) \|\| Texas Instrum. Deutschland GmbH, Freising, Germany (Menz, P.) \|\| Texas Instrum., Dallas, TX, USA (Yasuda, H.)
Abstract	We study the accumulated degradation of SiGe HBTs under time-dependent mixed-mode stress using a new physics-based TCAD degradation model that simulates hot carrier generation and propagation to oxide interfaces, resulting in trap formation. We calibrate the avalanche generation and also do a multipoint calibration of damage on the I-V output plane to accurately predict the accumulated stress damage for a single device over multiple bias points. Looking at the region of the output plane dominated by trap formation, we show that accumulation of traps can be path-independent as long as trap availability is not limiting. We demonstrate this with good correlation between simulation and measurement.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	179
Ending Page	182
File Size	255659
Page Count	4
File Format	PDF
ISBN	9781479901265
ISSN	10889299
e-ISBN	9781479901296
DOI	10.1109/BCTM.2013.6798170
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Degradation Mathematical model Calibration Hot carriers Current measurement Predictive models avalanche generation mixed-mode stress SiGe HBT reliability degradation bipolar transistor impactionization hot carriers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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