NDLI: A highly-efficient BiCMOS cascode Class-E power amplifier using both envelope-tracking and transistor resizing for LTE-like applications

Content Provider	IEEE Xplore Digital Library
Author	Yan Li Ruili Wu Lopez, J. Lie, D.Y.C.
Copyright Year	2011
Description	Author affiliation: Dept of Electrical and Computer Engineering, Texas Tech University, Lubbock, 79409, USA (Yan Li; Ruili Wu; Lopez, J.; Lie, D.Y.C.)
Abstract	This paper presents the design of a SiGe differential cascode power amplifier (PA) to perform the envelope-tracking (ET) along with transistor resizing for efficiency enhancement for the 16QAM LTE. A new parallel-circuit class-E PA model is developed to analyze and design the cascode PA. The analytic results are compared with SPICE simulation and measurement data to provide circuit design insights. Measurement shows the ET-based PA system reaches an overall power-added-efficiency (PAE) of 38% at its 1 dB compression point (P1dB) of 22 dBm for its high power mode. Additionally, at the low power mode, some of the transistor cells can be disabled by the integrated MOSFET switches, and the overall PAE is improved by 4–5% at ≥4 dB back-off from its P1dB. This ET-based cascode PA satisfies the LTE 16QAM linearity specs without needing predistortions.
Starting Page	142
Ending Page	145
File Size	586567
Page Count	4
File Format	PDF
ISBN	9781612841656
ISSN	10889299
e-ISBN	9781612841663
DOI	10.1109/BCTM.2011.6082767
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Silicon germanium Power amplifiers Modulation CMOS integrated circuits BiCMOS integrated circuits Linearity transistor resizing SiGe BiCMOS power amplifier (PA) envelope-tracking (ET) LTE parallel-circuit class-E PA model
Content Type	Text
Resource Type	Article

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