NDLI: Statistical eye analysis implemented in VHDL-AMS

Please wait, while we are loading the content...

2010 IEEE International Behavioral Modeling and Simulation Workshop

2009 IEEE Behavioral Modeling and Simulation Workshop

2008 IEEE International Behavioral Modeling and Simulation Workshop

2007 IEEE International Behavioral Modeling and Simulation Workshop

System design oriented RF block modeling : When top-down reaches bottom-up

Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch

Modeling heterogeneous systems using SystemC-AMS case study: A Wireless Sensor Network Node

An efficient bottom-up extraction approach to build the behavioral model of switched-capacitor ΔΣ modulator

Architecture-level thermal behavioral models for quad-core microprocessors

Automatic mixed-signal design verification instrumentation with observation specification language

High-performance model compilation for complex behavioral models

Certify— A characterization and validation tool for behavioral models

Event driven analog modeling of RF frontends

RF library based on block diagram and behavioral descriptions

Circuit reliability simulation based on Verilog-A

Statistical eye analysis implemented in VHDL-AMS

A mixed-mode behavioral model of a Controller-Area-Network bus transceiver: a case study

Efficient modeling of single event transients directly in compact device models

A mathematica-based approach to designing receiver and transmitter gain tables

Behavioral modeling of a charge pump voltage converter for SoC functional verification purposes

Modeling and analysis of biological cells in DRAM implementation

Simul’Elec, a Delphi written simulator for power Electrical Engineering, using VHDL-AMS modeling

Behavioral models of frequency pulling in oscillators

A generic VHDL-AMS behavioral model physically accounting for typical analog non-linear output behavior

An accurate PLL behavioral model for fast Monte Carlo analysis under process variation

AMS modeling of controlled switch for design optimization of capacitive vibration energy harvester

An integrated approach to energy harvester modeling and performance optimization

Multilevel modeling of integrated power harvesting system using VHDL-AMS and SPICE

Macro-modeling of liquid crystal cell with VerilogA

A unified electrical SPICE model for piezoelectric transducers

An efficient and accurate MEMS accelerometer model with sense finger dynamics for applications in mixed-technology control loops

Worst-case modeling and simulation of an automotive throttle in VHDL-AMS

Behavioral simulation of biological neuron systems using VHDL and VHDL-AMS

Phase change memory modeling using Verilog-A

2006 IEEE International Behavioral Modeling and Simulation Workshop

BMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005.

Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference, 2004. BMAS 2004.

Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation

Proceedings of the 2002 IEEE International Workshop on Behavioral Modeling and Simulation, 2002. BMAS 2002.

Proceedings of the Fifth IEEE International Workshop on Behavioral Modeling and Simulation. BMAS 2001 (Cat No.01TH8601)

Proceedings 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation

Statistical eye analysis implemented in VHDL-AMS

Content Provider	IEEE Xplore Digital Library
Author	Muranyi, A.
Copyright Year	2007
Description	Author affiliation: Mentor Graphics Corp., Redmond (Muranyi, A.)
Abstract	This paper introduces the reader to a VHDL-AMS (an IEEE-endorsed standard modeling language, standard 1076.1) implementation of the basic Statistical Eye Analysis algorithm. The main purpose of this paper is to show how such algorithms can be implemented using VHDL-AMS, and not to discuss the derivation details, novelty or usefulness of the algorithms. The example code that accompanies this paper is fully functional, but many more features and refinements need to be added to it to make it ready for real-world design work. The topic of this paper is essentially a continuation of the presentation given by the author on "Peak Distortion Analysis Implemented in VHDL-AMS".
Starting Page	64
Ending Page	66
File Size	171571
Page Count	3
File Format	PDF
ISBN	9781424415670
DOI	10.1109/BMAS.2007.4437526
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Algorithm design and analysis Bit error rate Mathematical model Distributed parameter circuits Computer languages Circuit simulation Pulse generation Resistors Inductors
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in