NDLI: Initialization of mixed-signal systems in VHDL-AMS

Content Provider	IEEE Xplore Digital Library
Author	Ruan, K.G.
Copyright Year	2001
Description	Author affiliation: Avant! Corp., Beaverton, OR, USA (Ruan, K.G.)
Abstract	Complex systems, such as telecommunication systems, control systems, etc., most often consist of both analog circuitry and digital circuitry. It is more efficient in simulation to represent such complex systems as mixed signal systems that both analog description and digital description are adopted. VHDL-AMS is an IEEE standard which is designed to describe multi-discipline, mixed-signal systems. Three port types are supported in VHDL-AMS including terminal, quantity and signal. Properties of a port vary significantly with port type. It is crucial to have a good understanding of these properties which have significant impact on the behavior in simulation. DC analysis is the most essential analysis for mixed signal systems that leads the system to an appropriate initial point for transient analysis. This paper first discusses the port properties of all three port types. Then, the important language features in VHDL-AMS for mixed-signal system description are discussed. A generic model for mixed-signal systems and the criteria that a DC solution of a mixed-signal system is reached is presented. Then, analysis of the interaction between different signal types in DC analysis is presented to explore the common issues in mixed-signal system simulation. Finally, with an interface model as an example, DC simulation results of a mixed-signal system are presented and analyzed. The techniques for modeling mixed signal systems in VHDL-AMS are summarized.
Sponsorship	IEEE Circuits & Syst. Soc
Starting Page	53
Ending Page	58
File Size	570825
Page Count	6
File Format	PDF
ISBN	0780372913
DOI	10.1109/BMAS.2001.962497
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal analysis Computational efficiency Energy conservation Logic Control systems Telecommunication control Circuit simulation Transient analysis Analytical models Hydraulic systems
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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