NDLI: Pre-determining comparative tests and utilizing signal levels to perform accurate diagnostics

Content Provider	IEEE Xplore Digital Library
Author	Kirkland, L.
Copyright Year	2009
Description	Author affiliation: WesTest Engineering, 810 W. Shepard Lane, Farmington, Utah 84025, USA (Kirkland, L.)
Abstract	Standard diagnostic schemes don't do enough analysis to focus in on the actual cause of a test failure. Often measurements will be border-line on test sequences prior to an actual test failure. These border-line measurements can be used to aid in the determination of an actual fault. An actual fault and the associated test that should detect that fault can be deceiving. The specific test in question can pass but be right on the border-line. The failure might not show up in testing until a later test is performed. This later test assumes all the prior tests passed and therefore the circuitry associated with these prior tests is good. This is not necessarily the case if some of the output measurements prior to the actual failing test were right on the border-line. What can we do? Take advantage of the order in which the faults are $simulated^{1}.$ We should structure our TPSs such that a review of preliminary tests should be evaluated before the R/R component list is presented. The review of the preliminary test can be rather straight forward. We can look at signals that are within 8–10% of the lower or upper limit. We can then use an inter-related test scheme to evaluate the test(s) that can be associated with the actual failing test. This paper will use an example TPS and show how a test scheme and an evaluation scheme can be used to determine the PCOF. The paper will show actual measurements and how these measurements can be evaluated to determine the actual cause of a failure.
Starting Page	343
Ending Page	347
File Size	394253
Page Count	5
File Format	PDF
ISBN	9781424449804
ISSN	10887725
DOI	10.1109/AUTEST.2009.5314091
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Circuit testing Circuit faults System testing Watches Failure analysis Signal analysis Performance analysis Electrical fault detection Fault detection
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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