NDLI: Scalable-distributed-arbitration ATM switch supporting multiple QoS classes

Content Provider	IEEE Xplore Digital Library
Author	Oki, E. Yamanaka, N. Nabeshima, M.
Copyright Year	1999
Description	Author affiliation: NTT Service Syst. Labs., Tokyo, Japan (Oki, E.)
Abstract	This paper proposes a multi-QoS scalable-distributed-arbitration (MSDA) ATM switch that supports both the high-priority class and the low-priority class under the head-of-line-priority discipline. It has a crosspoint buffer and a transit buffer, each consisting of a high-priority buffer and a low-priority buffer. Arbitration is executed between the crosspoint buffer and the transit buffer in a distributed manner. The MSDA switch extends the advantage of our previously proposed single-QoS scalable-distributed-arbitration (SSDA) switch. It is expandable while permitting high output-line speeds due to the distributed arbitration. The SSDA switch has a problem when its delay-time-based cell selection mechanism is applied to the low-priority class due to the limitation of the number of bits for the delay measure in the cell overhead. We solved this problem by introducing a distributed-ring-arbiter-based cell selection mechanism at each crosspoint for the low-priority class. The low-priority transit buffer at each crosspoint has virtual queues in accordance with the upper input ports. Cells for the low-priority class are selected by distributed ring arbitration among the low-priority crosspoint buffer and the virtual queues at the low-priority transit buffer. Simulations confirm that the MSDA switch ensures fairness in terms of delay time for the high-priority class, while it ensures fairness in terms of throughput for the low-priority class.
Starting Page	319
Ending Page	324
File Size	486757
Page Count	6
File Format	PDF
ISBN	4885521645
DOI	10.1109/ATM.1999.786875
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electronics, Information and Communication Engineers (IEICE)
Subject Keyword	Switches Asynchronous transfer mode Communication switching Delay effects Throughput Multimedia communication HDTV Laboratories Electronic mail Communication networks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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