NDLI: VC-merge capable scheduler design

Content Provider	IEEE Xplore Digital Library
Author	Chow, H.K. Leon-Garcia, A.
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada (Chow, H.K.)
Abstract	VC merging allows VC to be mapped onto the same VC label. It provides a scalable solution for network growth. It enables features such as stream merging in MPLS and RSVP wildcard filter to be efficiently supported over ATM. It also plays an important role in providing multipoint-to-multipoint multicast and share-tree multicasting paradigm. VC merging involves distinguishing cells from an identical merged VC label. Various approaches have been proposed to help this identification process. However, most of them incur additional buffering, protocol overhead and/or variable delay. They make the provision of QoS difficult to achieve. In this paper, we propose a novel merge-capable scheduler to support VC merging. The proposed scheduler consists of a core scheduler and a number of sub-queue sequencers forming a 2-level hierarchical structure. Using the proposed merge-capable scheduler, we can uniquely identify incoming cells while: (1) allowing cell cut-through forwarding and interleaving; (2) maintaining per-flow QoS; and (3) requiring no additional buffer and protocol overhead. We show analytically that the scheduler can guarantee a worst-case fairness and deliver a worst-case delay bound. We further analyze the scheduler performance in term of the service received by a queue and the average queuing delay experienced by a cell. The results indicate that the amount of services is fairly distributed among merging and non-merging flows according to their reservations. Moreover, the proposed merge-capable scheduler performs equally as well as its non-merging counterpart when reservations are highly utilized, even though it may introduce a minimal additional delay when utilization is low.
Starting Page	153
Ending Page	160
File Size	717856
Page Count	8
File Format	PDF
ISBN	4885521645
DOI	10.1109/ATM.1999.786851
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electronics, Information and Communication Engineers (IEICE)
Subject Keyword	Switches Merging Virtual colonoscopy Filters Asynchronous transfer mode Delay Multiprotocol label switching Protocols Queueing analysis Proposals
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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