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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wittmann, R. Bierbaum, D. Schardein, W. Matei, E. |
| Copyright Year | 1999 |
| Description | Author affiliation: Nokia Res. Center, Bochum, Germany (Wittmann, R.) |
| Abstract | A flexible generator for fast and accurate trimless potentiometric digital-to-analog converters has been developed. The chosen implementation style focuses on reusability. A conventional mixed signal design framework has been selected for implementation. An implemented resistor optimization technique guarantees an optimum yield in a given technology process without the need for error correction. Digital-to-analog converters with resolution up to 16 bit can be generated. For a digital radio system a 10-bit 85 MHz, and a 12-bit 100 kHz DAC were fabricated in a 0.35 /spl mu/m standard CMOS process with same generator. The design time coming from high level specification down to GDSII-level was less than 2 weeks for the high speed 10-bit converter, for the slow 12 bit converter less than 3 days. |
| Starting Page | 404 |
| Ending Page | 408 |
| File Size | 349151 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780356322 |
| DOI | 10.1109/ASIC.1999.806543 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-09-18 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Digital communication Resistors CMOS technology Error correction Digital-analog conversion Signal resolution CMOS process Analog-digital conversion Signal processing Signal design |
| Content Type | Text |
| Resource Type | Article |
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