NDLI: The active pixel CID-a new approach in electronic imaging

Content Provider	IEEE Xplore Digital Library
Author	Lungu, G. Fuller, L. Ninkov, Z. Hsu, K.W.
Copyright Year	1999
Description	Author affiliation: Rochester Inst. of Technol., NY, USA (Lungu, G.)
Abstract	A new type of sensor has been developed for applications in high radiation environments such as space, nuclear reactors or for machine vision. In this paper we present the pixel structure, fabrication cycle and measured performance of a family of active pixel charge injection devices (AP-CID) designed in PMOS and respectively CMOS technology. A simple 8/spl times/8 prototype was developed in 1996. This was followed by a 40/spl times/54 array having 90 /spl mu/m pixel size. This device has address decoders integrated on chip and, a transfer gate included in each pixel in order to eliminate the feed-through noise. These circuits were fabricated at RIT using a 6 /spl mu/m PMOS double polysilicon technology. A third 128/spl times/128 array having 41 /spl mu/m pixel size has been designed and manufactured at a commercial foundry using 2 /spl mu/m CMOS technology. The on-chip decoders allow resetting of selective regions of the chip. The circuits showed low power consumption, good linearity and a dynamic range in excess of 70 dB.
Starting Page	293
Ending Page	298
File Size	495271
Page Count	6
File Format	PDF
ISBN	0780356322
DOI	10.1109/ASIC.1999.806522
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-09-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel CMOS technology Space technology Integrated circuit technology Decoding Nuclear electronics Machine vision Fabrication Current measurement Charge measurement
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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