NDLI: Design of a hybrid reconfigurable coprocessor

Content Provider	IEEE Xplore Digital Library
Author	Xiang Wang Su Zhang Wei Ni Yukun Song Yanhui Yang Jichun Bu
Copyright Year	2013
Description	Author affiliation: Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China (Xiang Wang; Su Zhang; Wei Ni; Yukun Song) \|\| LZeal Inf. Technol. Co., Ltd., Wuxi, China (Yanhui Yang; Jichun Bu)
Abstract	Reconfigurable processors are noticeable for their flexibility and high computation performance. Combining a general purpose processor with a reconfigurable coprocessor can improve the overall system performance. As wide range of algorithms have appeared due to the increasing complexity of applications, the general purpose processors undertake more serial computing tasks, which also leads to more time consumption during the task switching. Meanwhile, higher bandwidth demand comes with the increasing of computation efficiency. A hybrid reconfigurable coprocessor has been proposed here, which reduces its dependence on the general purpose processor. Optimized L2-cache has been designed to enhance the data locality and reusability. The proposed coprocessor based on an FPGA has been implemented which can operate at 100MHz. Experimental results show that much better performance has been achieved with this proposed coprocessor.
Sponsorship	IEEE Beijing Sect.
Starting Page	1
Ending Page	4
File Size	559850
Page Count	4
File Format	PDF
ISBN	9781467364157
ISSN	2162755X
e-ISBN	9781467364171
DOI	10.1109/ASICON.2013.6811980
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jacobian matrices Coprocessors Program processors Algorithm design and analysis Arrays Pipelines Context
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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