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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wei Huang Kahng, A.B. |
| Copyright Year | 1997 |
| Description | Author affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA (Wei Huang) |
| Abstract | We describe a "topology advisor" for routing of critical (multisource) buses in building-block design. The tool accepts as input a block layout, a two-layer routing cost structure superposed over the block layout, terminal locations for a multi-source bus, and source-sink delay upper bound (linear or Elmore delay) constraints for all terminal pairs. The b best routing solutions (b a user parameter) that satisfy all constraints are returned. Efficient implementations of exhaustive search are used to guarantee optimal results when practical, and otherwise yield fast, high-quality results (if the problem is large or if the constraints are loose). Practical features include: (i) modeling of per-region and per-layer routing costs, (ii) routing to terminals located inside blocks, (iii) optional splitting of k-pin bus routes when the optimal routing passes through narrow channels, and (iv) heuristic speedups based on clustering and sampling. |
| Starting Page | 210 |
| Ending Page | 214 |
| File Size | 685261 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780342836 |
| ISSN | 10630988 |
| DOI | 10.1109/ASIC.1997.617007 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-09-07 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Delay lines Computer science Upper bound Repeaters Cost function Sampling methods Process planning Technology planning Process design |
| Content Type | Text |
| Resource Type | Article |
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