NDLI: A robust CMOS logic technique for building high frequency circuits with efficient pipelining

Content Provider	IEEE Xplore Digital Library
Author	Gayles, E. Acken, K. Owens, R.M. Irwin, M.J.
Copyright Year	1997
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA (Gayles, E.)
Abstract	Current fine grain pipelining techniques, such as True Single-Phase, allow for high frequency circuit design at the cost of significant latency per operation. On the other hand, low latency designs require complex circuitry within pipeline stages, which is not feasible when designing high clock frequency systems. In this paper, we propose a novel CMOS circuit technique that allows both high frequency circuits and low cycle latency per operation. Our technique differs from other logic families that have attempted to provide the same advantages by being more robust in the presence of process variations and signal coupling. To show the feasibility of our circuit technique, we also present a 64 bit carry-lookahead adder using this circuit technique that is capable of calculating a 64 bit add every 2.0 nanoseconds.
Starting Page	168
Ending Page	172
File Size	511319
Page Count	5
File Format	PDF
ISBN	0780342836
ISSN	10630988
DOI	10.1109/ASIC.1997.616999
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-09-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS logic circuits Robustness CMOS technology Frequency Delay Pipeline processing Buildings Circuit synthesis Costs Clocks
Content Type	Text
Resource Type	Article

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