NDLI: A bit serial linear array DFT

Content Provider	IEEE Xplore Digital Library
Author	Allen, G. Denyer, P. Renshaw, D.
Copyright Year	1984
Description	Author affiliation: James Cook University of North Queensland, Australia (Allen, G.)
Abstract	A Linear array which computes the DFT in a pipelined fashion is described. The algorithm is derived from the batch processing array proposed by H.T. Kung [1] but has been modified to allow continuous operation. This computation of the DFT is a complex polynomial evaluation on the unit circle using Horner's method having the data for the polynomial coefficients. Data and the N-th complex roots of unity are input at one end of the array and the DFT sequence is output from the other. The polynomial coefficients are stored in successive modules in the array and a new batch is latched successively with a synchronising signal. In its simplest form the design has a single system part which is replicated N times for an N-point transform. For time multiplexed modules the system throughput and hardware can be optimised for given applications. A bit serial layout for 6 micron NMOS VLSI has been designed and simulated using the FIRST silicon compiler at the University of Edinburgh.
Starting Page	230
Ending Page	233
File Size	120248
Page Count	4
File Format	PDF
DOI	10.1109/ICASSP.1984.1172761
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1984-03-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete Fourier transforms Signal processing algorithms Delay Equations Polynomials Hardware Very large scale integration Systolic arrays Silicon compiler Fourier transforms
Content Type	Text
Resource Type	Article

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