NDLI: Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

Content Provider	IEEE Xplore Digital Library
Author	Diken, E. O'Riordan, M.J. Jordans, R. Jozwiak, L. Corporaal, H. Moloney, D.
Copyright Year	2015
Description	Author affiliation: Eindhoven Univ. of Technol., Eindhoven, Netherlands (Diken, E.; Jordans, R.; Jozwiak, L.; Corporaal, H.) \|\| Movidius Ltd., Dublin, Ireland (O'Riordan, M.J.; Moloney, D.)
Abstract	The degree of DLP parallelism in applications is not fixed and varies due to different computational characteristics of applications. On the contrary, most of the processors today include single-width SIMD (vector) hardware to exploit DLP. However, single-width SIMD architectures may not be optimal to serve applications with varying DLP and they may cause performance and energy inefficiency. We propose the usage of VLIW processors with multiple native vector-widths to better serve applications with changing DLP. SHAVE is an example of such VLIW processor and provides hardware support for the native 32-bit and 128-bit wide vector operations. This paper researches and implements the mixed-length SIMD code generation support for SHAVE processor. More specifically, we target generating 32-bit and 128/64-bit SIMD code for the native 32-bit and 128-bit wide vector units of SHAVE processor. In this way, we improved the performance of compiler generated SIMD code by reducing the number of overhead operations and by increasing the SIMD hardware utilization. Experimental results demonstrated that our methodology implemented in the compiler improves the performance of synthetic benchmarks up to 47%.
Starting Page	181
Ending Page	188
File Size	657408
Page Count	8
File Format	PDF
ISSN	2160052X
e-ISBN	9781479919253
DOI	10.1109/ASAP.2015.7245732
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-27
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Hardware Program processors Assembly Computer architecture VLIW Support vector machines
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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