NDLI: Customizable coarse-grained energy-efficient reconfigurable packet processing architecture

Content Provider	IEEE Xplore Digital Library
Author	Badawi, M. Hemani, A. Zhonghai Lu
Copyright Year	2014
Description	Author affiliation: KTH R. Inst. of Technol., Stockholm, Sweden (Badawi, M.; Hemani, A.; Zhonghai Lu)
Abstract	In this paper, we present a highly customizable and rapidly reconfigurable multi-core packet processing architecture that provides energy and area efficiency while retaining flexibility. Presented architecture with its agile reconfigurability permits time-critical adaptability where resources can be re-clustered at run time in few cycles, hence, maintaining efficiency if requirements of the use-case change. We elaborate the flexibility and adaptability of our architecture and we report its evaluation results. For evaluation, we performed the widely-used UDP/IP and we compared our proposed architecture to low-power 32-bit general purpose processors, a custom ASIC implementation and a programmable protocol processor. Compared to GPP-based solutions, our architecture is 20-34 times more energy efficient while providing 2.4-4.1 times higher throughput. While retaining the programmability, the proposed solution achieved 78% of the energy efficiency of hardwired ASIC implementation. Compared to a programmable protocol processor, our solution has 2.6 times more throughput and requires only a third of the gate count. lastly, we quantified the worst-case time and average-case time required for time-critical adaptability when reconfiguration occurs during a real-life Voice-Over IP traffic.
Sponsorship	IEEE Comput. Soc.
Starting Page	30
Ending Page	35
File Size	202256
Page Count	6
File Format	PDF
ISBN	9781479936090
ISSN	2160052X
DOI	10.1109/ASAP.2014.6868627
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-18
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Program processors Application specific integrated circuits IP networks Time factors Delays Protocols
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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