NDLI: Control Scheme for a CGRA

Content Provider	IEEE Xplore Digital Library
Author	Shami, M.A. Hemani, A.
Copyright Year	2010
Abstract	Ability to instantiate low cost and agile FSMs that can implement an arbitrary parallelism and combine such FSMs in a chain and in a hierarchy is one of the key differentiating factors between the ASICs and MPSOCs. CGRAs that have been reported in literature, like MPSOCs, also lack this ASIC like ability. The downside of ASICs is their lack of reuse and high engineering cost. We present a CGRA architecture that retains the programmability of CGRA and yet has the ASIC like ability to construct a) arbitrarily parallel data-path/FSM combine, b) chain an arbitrary number of such FSMs and c) create a hierarchy of such chains. We present in detail the architecture of such a control scheme and illustrate its use for an example composed of FFT and FIRs. We quantify the benefits of our approach by benchmarking for energy-delay product against a) ASICs (4.8X worse), b) a state-of-the-art CGRA (4.58X better) and FPGAs (63.95X better).
Starting Page	17
Ending Page	24
File Size	1331076
Page Count	8
File Format	PDF
ISBN	9781424482870
ISSN	15506533
DOI	10.1109/SBAC-PAD.2010.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-27
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Switches Registers Program processors Field programmable gate arrays Parallel processing Delay Reconfigurable Architecture CGRA Dynamically Reprogrammable Resource Arrays
Content Type	Text
Resource Type	Article

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