NDLI: Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS

Content Provider	IEEE Xplore Digital Library
Author	Currie, S.M. Schumacher, P.R. Gilbert, B.K. Swartzlander, E.E. Randall, B.A.
Copyright Year	2002
Description	Author affiliation: Mayo Found., Rochester, MN, USA (Currie, S.M.)
Abstract	The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.
Sponsorship	IEEE Comput. Soc. Tech. Committee on VLSI
Starting Page	335
Ending Page	343
File Size	1557560
Page Count	9
File Format	PDF
ISBN	0769517129
ISSN	21600511
DOI	10.1109/ASAP.2002.1030732
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-07-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fast Fourier transforms Random access memory Application specific integrated circuits Computer interfaces Distributed computing Computer architecture CMOS technology Pipelines Clocks Design engineering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design and implementation of a two-dimensional fast Fourier transform chip

Design and implementation of a two-dimensional fast Fourier transform chip

Embedded HIMOS(R) flash memory in 0.35 /spl mu/m and 0.25 /spl mu/m CMOS technologies

A parallel-pipelined processor for fast fourier transform

A fast, pipelined implementation of a two-dimensional inverse discrete cosine transform

An architecture for a radix-4 modular pipeline fast Fourier transform

Pipelined architecture for fast CMOS buffer RAMs

A reconfigurable pipelined ADC in 0.18 /spl mu/m CMOS

An injection locked, RF powered, telemetry IC in 0.25 /spl mu/m CMOS

Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS

Similar Documents

Design and implementation of a two-dimensional fast Fourier transform chip

Design and implementation of a two-dimensional fast Fourier transform chip

Embedded HIMOS(R) flash memory in 0.35 /spl mu/m and 0.25 /spl mu/m CMOS technologies

A parallel-pipelined processor for fast fourier transform

A fast, pipelined implementation of a two-dimensional inverse discrete cosine transform

An architecture for a radix-4 modular pipeline fast Fourier transform

Pipelined architecture for fast CMOS buffer RAMs

A reconfigurable pipelined ADC in 0.18 /spl mu/m CMOS

An injection locked, RF powered, telemetry IC in 0.25 /spl mu/m CMOS

Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS