NDLI: Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors

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2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors

ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors

2008 International Conference on Application-Specific Systems, Architectures and Processors

2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)

IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors

Nanocomputing with delays

Compositional technique for synthesising multi-phase regular arrays

A compile time based approach for solving out-of-order communication in Kahn process networks

Model-based exploration of the design space for heterogeneous systems on chip

A component architecture for FPGA-based, DSP system design

Low power memory design

Reduced power consumption for MPEG decoding with LNS

A model-based methodology for application specific energy efficient data path design using FPGAs

Design space exploration for energy-efficient secure sensor network

High-radix logarithm with selection by rounding

An analysis of the CORDIC algorithm for direct digital frequency synthesis

Evaluating products of nonlinear functions by indirect bipartite table lookup

Efficient conversion from binary to multi-digit multi-dimensional logarithmic number systems using arrays of range addressable look-up tables

Predictable instruction caching for media processors

A mathematical model of trace cache

Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip

A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors

Fast radix-4 retimed division with selection by comparisons

PAPA - packed arithmetic on a prefix adder for multimedia applications

A combined interval and floating-point comparator/selector

Reviewing 4-to-2 adders for multi-operand addition

Implications of programmable general purpose processors for compression/encryption applications

Design and evaluation of a multimedia computing architecture based on a 3D graphics pipeline

Refining instruction set architecture for high-performance multimedia processing in constrained environments

Polynomial evaluation on multimedia processors

Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter

Instruction stream mutation for non-deterministic processors

A novel pipelined threads architecture for AES encryption algorithm

On the propagation of faults and their detection in a hardware implementation of the Advanced Encryption Standard

Matrix engine for signal processing applications using the logarithmic number system

A VLSI architecture for object recognition using tree matching

Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS

Optical network reconfiguration for signal processing applications

New results on array contraction [memory optimization]

A CORBA-based GIS-T for ambulance assignment

Advances in bit width selection methodology

Tradeoffs between quality of results and resource consumption in a recognition system

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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