NDLI: A dynamically reconfigurable wavefront array architecture for evaluation of expressions

Content Provider	IEEE Xplore Digital Library
Author	Hartenstein, R.W. Kress, R. Reinig, H.
Copyright Year	1994
Description	Author affiliation: Kaiserslautern Univ., Germany (Hartenstein, R.W.; Kress, R.; Reinig, H.)
Abstract	A reconfigurable wavefront array rDPA (reconfigurable datapath architecture) for evaluation of any arithmetic and logic expression is presented. Introducing a global I/O bus to the array simplifies the use as a coprocessor in a single bus oriented processor system. Fine grained parallelism is achieved using simple reconfigurable processing elements which are called datapath units (DPUs). The word-oriented datapath simplifies the mapping of applications onto the architecture. Pipelining is supported by the architecture. It is extendible to arbitrarily large arrays and dynamically in-circuit reconfigurable. The programming environment allows automatic mapping of the operators from high level descriptions. The corresponding scheduling techniques for I/O operations are explained. The rDPA can be used as reconfigurable ALU for bus oriented host based systems as well as for rapid prototyping of high speed datapaths.<>
Starting Page	404
Ending Page	414
File Size	722088
Page Count	11
File Format	PDF
ISBN	0818665173
ISSN	10636862
DOI	10.1109/ASAP.1994.331785
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-22
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Logic arrays Coprocessors Pipeline processing Programming environments Computer architecture Application software Arithmetic Reconfigurable logic Parallel processing
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture

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