NDLI: Modelling Latency-Insensitive Systems in CSP

Content Provider	IEEE Xplore Digital Library
Author	Kapoor, H.K.
Copyright Year	2007
Description	Author affiliation: Dhirubhai Ambani Inst. of Inf. & Commun. Technol., Gandhinagar, (Kapoor, H.K.)
Abstract	With the advance in semiconductor technology we are able to pack more and more devices on a single chip. However, the threat comes from the long interconnect wires whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency due the long interconnects, we require the IP cores to be latency-insensitive (LI). Design and validation of LI design is studied in L.P. Cartoni, et al., (1999), L.P. Cartoni, et al.,(2001), and T. Chelcea, et al., (2004). Generalised latency-insensitive systems, design of connecting FIFOs and other communication protocols appear in T. Chelcea, et al.,(2006), S. Dasgupta, et al., (2006), D. Potop-Butucaru, et al., (2006), and M. Singh, et al., (2003). Process algebras provide a well-studied framework for modelling and verifying concurrent systems. In this work we try to address the problem of long interconnects by modelling the latency insensitive protocol in the discrete time version of CSP. Time is modelled in terms of events occurring at regular intervals, modelled by the event took.
Starting Page	231
Ending Page	232
File Size	94618
Page Count	2
File Format	PDF
ISBN	076952902X
ISSN	15504808
DOI	10.1109/ACSD.2007.54
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-10
Publisher Place	Slovakia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Protocols Communications technology CMOS technology Wires Joining processes Algebra Computational modeling Interleaved codes Concurrent computing
Content Type	Text
Resource Type	Article

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