NDLI: Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector

Content Provider	IEEE Xplore Digital Library
Author	Guan Yu Lafruit, G. Schelkens, P.
Copyright Year	2007
Description	Author affiliation: Vrije Univ. Brussel, Brussels (Guan Yu)
Abstract	The Plessey corner detector is a key technological component in scene analysis, stereo matching, and object tracking. Due to its high computation complexity, earlier fast implementations mainly focused on hardware implementations. This paper explores the viability of a multi-processor software implementation. A scalable task partitioning for efficiently mapping the Plessey algorithm on a multi-processor platform is proposed. The task partition ensures platform scalability, low inter-processor communication overhead and a well-balanced workload in each task. In addition, a multilevel buffering scheme is presented, minimizing the external memory accesses in each task to one image pixel read per calculated corner response value. The effectiveness of the proposed task partition and buffering scheme has been verified on (i) a cycle accurate simulator with shared memory and (ii) a multiple-TI-C64 DSP board using a message passing paradigm. The proposed solution combines good platform scalability with an additional 30% speedup gain over straightforward parallelization schemes.
Starting Page	120
Ending Page	126
File Size	341117
Page Count	7
File Format	PDF
ISBN	076952902X
ISSN	15504808
DOI	10.1109/ACSD.2007.58
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-10
Publisher Place	Slovakia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Partitioning algorithms Scalability Detection algorithms Filtering algorithms Image analysis Hardware Pixel Computational complexity Parallel processing
Content Type	Text
Resource Type	Article

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