NDLI: Novel integration technique for flip-chip bonding circuit in wafer scale packaging

Content Provider	IEEE Xplore Digital Library
Author	Young Seek Cho Drayton, R.F.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ. (Young Seek Cho; Drayton, R.F.)
Abstract	A novel integration technique for flip-chip bonding a circuit in wafer scale packaging is presented. The solder is a multilayered structure which consists of 95 at.% Sn and 5 at.% Au. The metal-to-metal bonding process was carried out around 230degC in air. The solder bond pads have an area of $625mum^{2}$ with the height of 2.3mum. To characterize the integration technique a variety of designs for a flip-chip interconnections are fabricated and measured for a flip-chip mounted coplanar waveguide (CPW). Modeled predictions of the design show significant performance improvement can be achieved by considering the impact of the substrate and associated parasitics on the mounted chip and transition region in the design. In this paper, we discuss design, modeling and measurement of wide band transition for flip chipped circuits in wafer scale packaging. A locally scaled flip-chip structure is proposed to compensate effective dielectric constant at the transition part of the interconnect
Sponsorship	Motorola Air Force Office of Sci. Res. ANSOFT
Starting Page	57
Ending Page	60
File Size	188894
Page Count	4
File Format	PDF
ISBN	1424401232
DOI	10.1109/APS.2006.1710451
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer bonding Packaging Integrated circuit interconnections Semiconductor device measurement Coplanar waveguides Semiconductor device modeling Tin Gold Bonding processes Predictive models
Content Type	Text
Resource Type	Article

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