NDLI: An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading

Content Provider	IEEE Xplore Digital Library
Author	Fard, S.F. Alimohammad, A. Cockburn, B.F.
Copyright Year	1967
Abstract	We present an ultracompact and fast hardware simulator for Rayleigh and Rician fading channels. To ensure numerical robustness and an efficient mapping onto hardware, the fading simulator uses the sum-of-sinusoids technique with N = 32 sinusoids added up to model each fading path. Fading samples are generated at a low rate and then are passed to an interpolator, which computes the final samples at the desired baseband rate. We propose a new time-multiplexed datapath that uses a differential approach. Instead of directly generating the fading samples, the datapath generates the discrete difference between fading samples. The proposed simulator is so compact that an entire 4 × 4 multiple-input-multiple-output (MIMO) fading channel can be implemented on a small fraction of a single field-programmable gate array (FPGA). On a Xilinx Virtex-4 XC4VLX200-11 FPGA, up to 1184 different paths can be simultaneously implemented while generating 1184 × 342 million 2 × 16-bit complex-valued fading samples per second.
Sponsorship	IEEE Vehicular Technology Society
Starting Page	2725
Ending Page	2734
Page Count	10
File Size	1348174
File Format	PDF
ISSN	00189545
Volume Number	59
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Rician channels Rayleigh channels Computational modeling Fading Hardware Field programmable gate arrays MIMO Frequency Wireless communication Robustness wireless channel simulator Fading simulator MIMO channel simulator multipath fading Rayleigh fading Rician fading spatiotemporarily-correlated fading
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Automotive Engineering Computer Networks and Communications Electrical and Electronic Engineering Aerospace Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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