NDLI: Packet Processing acceleration with a 3-stage programmable pipeline engine

Content Provider	IEEE Xplore Digital Library
Author	Papaefstathiou, I. Vlachos, K. Nikolaou, N. Zervos, N. Lawrence, V.B.
Copyright Year	1997
Abstract	In this letter, we present the architecture and implementation of a novel, 3-stage processing engine, suitable for deep packet processing in high-speed networks. The engine, which has been fabricated as part of a network processor, comprises of a typical RISC core and programmable hardware. To assess the performance of the engine, experiments with packets of various lengths have been performed and compared against the IXP1200 network processor. The comparison has revealed that for the case study shown in this letter, the proposed packet-processing engine is up to three times faster. Moreover, the engine is simple to be fabricated, less expensive than the corresponding hardware cores of IXP1200 and can be easily programmed for different networking applications.
Starting Page	183
Ending Page	185
Page Count	3
File Size	227752
File Format	PDF
ISSN	10897798
Volume Number	8
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acceleration Pipelines Search engines Data mining Hardware Reduced instruction set computing Protocols Telecommunication traffic Application specific integrated circuits Network address translation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Modeling and Simulation Computer Science Applications

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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