NDLI: High-Q capacitors implemented in a CMOS process for low-power wireless applications

Content Provider	IEEE Xplore Digital Library
Author	Hung, C.-M. Ho, Y.-C. Wu, I.-C. O, K.
Copyright Year	1963
Abstract	In a foundry 0.8-/spl mu/m CMOS process, low-cost capacitors with a measured Q factor of around 50 at 3 GHz and high intrinsic capacitance/area (/spl sim/200 nF/cm/sup 2/) were demonstrated. When extrapolated to 900 MHz, the Q factor is greater than 100. The capacitors use a poly-to-n-well MOS structure which has been commonly dismissed for high-Q applications due to the high n-well sheet resistance (/spl sim/1 k/spl Omega///spl square/). Utilizing the structure, a low-noise amplifier (LNA) with a resonant frequency of 960 MHz, power gain of 16.2 dB, 1-dB compression point (P/sub 1 dB/) of -5 dBm, and noise figure of 3.5 dB was demonstrated. Using a rule of thumb, the third-order harmonic intercept point (P/sub IP3/) was estimated to be 5 dBm from the P/sub 1 dB/ data. Despite concerns for nonlinearity of the capacitors, these results suggest that this capacitor structure could be used in LNA's with a large dynamic range.
Sponsorship	IEEE Microwave Theory and Techniques Society
Starting Page	505
Ending Page	511
Page Count	7
File Size	210263
File Format	PDF
ISSN	00189480
Volume Number	46
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process MOS capacitors Q factor Foundries Area measurement Capacitance measurement Q measurement Low-noise amplifiers Resonant frequency Gain
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering Radiation

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

A dual-band CMOS front-end with two gain modes for wireless LAN applications

Ultra-low dc power GaAs HBT S- and C-band low noise amplifiers for portable wireless applications

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

Low-power programmable gain CMOS distributed LNA

5-GHz CMOS wireless LANs

Resistive-Feedback CMOS Low-Noise Amplifiers for Multiband Applications

High-Q capacitors implemented in a CMOS process for low-power wireless applications

Similar Documents

A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors

A dual-band CMOS front-end with two gain modes for wireless LAN applications

Ultra-low dc power GaAs HBT S- and C-band low noise amplifiers for portable wireless applications

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

Low-power programmable gain CMOS distributed LNA

5-GHz CMOS wireless LANs

Resistive-Feedback CMOS Low-Noise Amplifiers for Multiband Applications

High-Q capacitors implemented in a CMOS process for low-power wireless applications