NDLI: A design concept of array heads

Content Provider	IEEE Xplore Digital Library
Author	Tang, D.D. Santini, H. Lee, R.E. Ju, K. Krounbi, M.
Copyright Year	1965
Abstract	This paper describes a novel design concept and experimental hardware data of array heads for close-packed track recording. The heads are batch fabricated on wafers in a linear fashion. These 60-turn thin-film inductive heads are designed with 6 /spl mu/m pitch helical coils and planar side-by-side P1/G/P2 yokes structure. The linear head array is placed along the upstream-to-downstream direction of the track. By skewing the array slightly off the track direction, each head of the array aligns to an individual track. In this case, the track pitch is about 5 /spl mu/m, which is the yoke height. With this head arrangement, even though a thermal expansion causes the head-to-head distance to increase along the upstream-downstream direction, it does not cause a thermal induced track misregistration problem. The increased head-to-head distance only affects the timing of signals between tracks, which can be compensated by the channel electronics. Thus, the thermal induced track misregistration problem is eliminated using this design. The guard bands between tracks are not necessary, and a close-packed track recording is possible. A state of the art head impedance of the 60-turn head is obtained: 11 /spl Omega/ and 0.40 /spl mu/H. The gap-to-gap pitch is 100 /spl mu/m. The overall head-to-head isolation is greater than 50 dB at 10 MHz. Such a large isolation is realized by suppressing the capacitive coupling between lead wires using a ground plane and grounded wall structures. The tight winding of the helical coils reduces the magnetic coupling between the heads.
Sponsorship	IEEE Magnetics Society
Starting Page	2397
Ending Page	2401
Page Count	5
File Size	109021
File Format	PDF
ISSN	00189464
Volume Number	33
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Magnetic heads Magnetic recording Sensor arrays Transistors Coils Thermal expansion High definition video HDTV Ferrites Costs
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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