NDLI: Inductance measurements of superconducting chip-to-package connectors suitable for Josephson LSI technology

Content Provider	IEEE Xplore Digital Library
Author	Jones, H. Herrell, D. Yao, Y.
Copyright Year	1965
Abstract	It is necessary in any interconnection scheme used in LSI to be able to pass high-speed pulses from chip-to-chip through the package with a minimum of distortion while at the same time maximizing the number of input/output connectors (I/O's) in large arrays of densely packed connectors. We have measured the inductances (both self and mutual) of chip-to-package connectors which were arranged in a peripheral row around the edge of the circuit chip. The largest self-inductance measured for an 8:1 ratio of I/O's to ground connectors is low enough so that signals with a 30 ps time constant propagate through the connector without significant distortion. The largest self-inductance ranges from 28 pH for the linear array of eight connectors between grounds to 19 pH for four connectors between grounds. These results indicate that the electrical properties of these connectors are satisfactory for the LSI technology application of Josephson devices.
Sponsorship	IEEE Magnetics Society
Starting Page	432
Ending Page	434
Page Count	3
File Size	256642
File Format	PDF
ISSN	00189464
Volume Number	15
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inductance measurement Connectors Large scale integration Inductors Superconducting transmission lines Equivalent circuits Bonding Niobium Wiring Electric variables measurement
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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