NDLI: Network-on-Chip for Turbo Decoders

Content Provider	IEEE Xplore Digital Library
Author	Qingqing Yang Xiaofang Zhou Sobelman, G.E. Xinxin Li
Copyright Year	1993
Abstract	The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure gives an improvement of 53% for HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC solutions.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	338
Ending Page	342
Page Count	5
File Size	1298173
File Format	PDF
ISSN	10638210
Volume Number	24
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2016-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Multiaccess communication Spread spectrum communication Computer architecture Routing Very large scale integration Complexity theory VLSI. Network-on-chip (NoC) turbo decoder VLSI
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures

Very Low-Complexity Hardware Interleaver for Turbo Decoding

Area-efficient high-speed decoding schemes for turbo decoders

A Network-on-Chip-based turbo/LDPC decoder architecture

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications

VLSI architectures for SISO-APP decoders

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Network-on-Chip for Turbo Decoders

Similar Documents

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures

Very Low-Complexity Hardware Interleaver for Turbo Decoding

Area-efficient high-speed decoding schemes for turbo decoders

A Network-on-Chip-based turbo/LDPC decoder architecture

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications

VLSI architectures for SISO-APP decoders

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Network-on-Chip for Turbo Decoders