NDLI: A reconfigurable block cryptographic processor based on VLIW architecture

Content Provider	IEEE Xplore Digital Library
Author	Wei, Li Xiaoyang, Zeng Longmei, Nan Tao, Chen Zibin, Dai
Copyright Year	2013
Abstract	An Efficient and flexible implementation of block ciphers is critical to achieve information security processing. Existing implementation methods such as GPP, FPGA and cryptographic application-specific ASIC provide the broad range of support. However, these methods could not achieve a good tradeoff between high-speed processing and flexibility. In this paper, we present a reconfigurable VLIW processor architecture targeted at block cipher processing, analyze basic operations and storage characteristics, and propose the multi-cluster register-file structure for block ciphers. As for the same operation element of block ciphers, we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme. The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations, but also realizes dynamic configuration for cryptographic processing units. It has been implemented with 0.18μm CMOS technology, the test results show that the frequency can reach 350MHz, and power consumption is 420mw. Ten kinds of block and hash ciphers were realized in the processor. The encryption throughput of AES, DES, IDEA, and SHA-1 algorithm is 1554Mbps, 448Mbps, 785Mbps, and 424Mbps respectively, the test result shows that our processor's encryption performance is significantly higher than other designs.
Starting Page	91
Ending Page	99
Page Count	9
File Size	1079945
File Format	PDF
ISSN	16735447
Volume Number	13
Issue Number	1
Language	English
Publisher	China Communications Magazine Co. Ltd.
Publisher Date	2016-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ciphers Registers Process control Encryption Text processing Decision support systems application-specific instruction-set Block Cipher VLIW processor reconfigurable
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A High Energy-Efficient Reconfigurable VLIW Symmetric Cryptographic Processor with Loop Buffer Structure and Chain Processing Mechanism

Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems

High-Throughput Area-Efficient Processor for Cryptography

Reconfigurable Feedback Shift Register Based Stream Cipher for Wireless Sensor Networks

VIPER: a VLIW integer microprocessor

A VLIW processor with reconfigurable instruction set for embedded applications

Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation

Security analysis and enhanced design of a dynamic block cipher

Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing

A reconfigurable block cryptographic processor based on VLIW architecture

Similar Documents

A High Energy-Efficient Reconfigurable VLIW Symmetric Cryptographic Processor with Loop Buffer Structure and Chain Processing Mechanism

Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems

High-Throughput Area-Efficient Processor for Cryptography

Reconfigurable Feedback Shift Register Based Stream Cipher for Wireless Sensor Networks

VIPER: a VLIW integer microprocessor

A VLIW processor with reconfigurable instruction set for embedded applications

Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation

Security analysis and enhanced design of a dynamic block cipher

Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing

A reconfigurable block cryptographic processor based on VLIW architecture