NDLI: High-Throughput Area-Efficient Processor for Cryptography

Content Provider	IET Digital Library
Author	Huo, Yuanhong Liu, Dake
Abstract	Cryptography circuits for portable electronic devices provide user authentication and secure data communication. These circuits should, achieve high performance, occupy small chip area, and handle several cryptographic algorithms. This paper proposes a highperformance ASIP (Application specific instruction set processor) for five standard cryptographic algorithms including both block ciphers (AES, Camellia, and ARIA) and stream ciphers (ZUC and SNOW 3G). The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption, 16.0 Gb/s for ZUC, and 32.0 Gb/s for SNOW 3G, etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm2 (65 nm). Compared with stateof-the-art VLSI designs, our design achieves high performance, low silicon cost, low power consumption, and sufficient programmability. For its programmability, our design can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to use. The product lifetime of our design can thus be extended.
Starting Page	514
Ending Page	521
Page Count	8
ISSN	10224653
Volume Number	26
e-ISSN	20755597
Issue Number	Issue 3, May (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/cje/26/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/cje.2017.03.004
Journal	Chinese Journal of Electronics
Publisher Date	2017-05-01
Access Restriction	Open
Rights Holder	© Chinese Institute of Electronics
Subject Keyword	AES Block Ciphers AES Encryption Application Specific Instruction Set Processor ARIA Block Ciphers Camellia Block Ciphers Cryptography Cryptography Circuit Frequency 1 GHz High-performance ASIP High-throughput Area-efficient Processor Instruction Sets Microprocessor Chips Microprocessors And Microcomputer Portable Electronic Device Secure Data Communication SNOW 3G Stream Ciphers User Authentication ZUC Stream Ciphers
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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