NDLI: Using Wafer Map Features to Better Predict Die-Level Failures in Final Test

Content Provider	IEEE Xplore Digital Library
Author	Seokho Kang Sungzoon Cho Daewoong An Jaeyoung Rim
Copyright Year	1988
Abstract	In semiconductor manufacturing, wafer fabrication is followed by chip assembly where individual dies are assembled as a packaged chip. In between, dies are tested in terms of their electrical properties and those which fail to pass the “wafer test” are filtered out. However, some faulty dies pass the test and cause a packaged chip to fail in the final test. The inaccuracy of the wafer test leads to waste in manufacturing time and cost. In this paper, we propose to predict the result of the final test at the die-level before assembly using wafer test items and four derivations concerning wafer map features: 1) distance of the die from the wafer center; 2) previous final yield at the die position; 3) wafer test fail rate for the adjacent dies; and 4) abnormalities of the wafer map pattern. We build prediction models with these variables using a random forest algorithm. Preliminary experimental results on actual data show that the use of these derived variables improves the prediction performance with a statistical significance, thus merits further investigation.
Sponsorship	IEEE Electron Devices Society IEEE Components, Packaging, and Manufacturing Technology Society IEEE Reliability Society IEEE Solid-State Circuits Society
Starting Page	431
Ending Page	437
Page Count	7
File Size	957364
File Format	PDF
ISSN	08946507
Volume Number	28
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Predictive models Semiconductor device modeling Input variables Probes Assembly Vegetation random forest die-level failure wafer map feature yield prediction final test wafer test Die-level failure
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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