NDLI: Built-in-Self-Test-Stacked 3-D Ring Oscillator Based on Through Silicon Vias

Content Provider	IEEE Xplore Digital Library
Author	Jin, C. Li, Y. Li, R. Hu, S. Ding, L. Li, H. Zhang, S.
Copyright Year	2011
Abstract	A 3-D ring oscillator integrated with through silicon vias (TSVs) is designed and fabricated for testing multilayer-stacked integrated circuits (ICs) with TSV. The proposed 3-D ring oscillator consists of 13 stages and 65-nm Complementary Metal-Oxide-Semiconductor Transistor (CMOS) dies with two current-starved inverters and via-last TSVs designed for the five middle layers of the 3-D ring oscillator. The two cascaded inverters are connected to the upside layer through a TSV and to the downside layer through a microbump. One chip with two inverters but without TSV is stacked in the top layer of the 3-D ring oscillator to realize the ring oscillator loop, and one logic chip with one inverter and via-middle TSVs are in the bottom of the ring oscillator. The characteristics of via-last and via-middle TSVs in the 3-D ring oscillator are analyzed based on the equivalent circuits. The oscillation frequency responses of the designed 3-D ring oscillator are measured finally to verify the design concept, and to assess the performance of the 3-D ring oscillator. The measured results demonstrate that the proposed 3-D ring oscillator is an attractive candidate for testing the stacked 3-D IC, and the effect of TSVs dominates the delay of the 3-D ring oscillator.
Starting Page	217
Ending Page	224
Page Count	8
File Size	3025639
File Format	PDF
ISSN	21563950
Volume Number	5
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ring oscillators Through-silicon vias Inverters Delays CMOS integrated circuits Capacitance via-middle TSV. 3-D integrated circuit (3-D IC) 3-D ring oscillator through silicon via (TSV) via-last TSV
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Built-in-self-test 3-D ring oscillator for stacked 3DIC

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)

A Thermal Isolation Technique Using Through-Silicon Vias for Three-Dimensional ICs

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis

Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies

A New Model for Through-Silicon Vias on 3-D IC Using Conformal Mapping Method

Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts

Contactless Test Access Mechanism for TSV-Based 3-D ICs Utilizing Capacitive Coupling

Built-in-Self-Test-Stacked 3-D Ring Oscillator Based on Through Silicon Vias

Similar Documents

Built-in-self-test 3-D ring oscillator for stacked 3DIC

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)

A Thermal Isolation Technique Using Through-Silicon Vias for Three-Dimensional ICs

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis

Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies

A New Model for Through-Silicon Vias on 3-D IC Using Conformal Mapping Method

Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts

Contactless Test Access Mechanism for TSV-Based 3-D ICs Utilizing Capacitive Coupling

Built-in-Self-Test-Stacked 3-D Ring Oscillator Based on Through Silicon Vias