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Content Provider | IEEE Xplore Digital Library |
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Author | Abou Qamar, N. Hatziadoniu, C.J. Haibo Wang |
Copyright Year | 1982 |
Abstract | Modern resolver-to-digital converters (RDCs) are typically implemented using DSP techniques to reduce hardware footprint and enhance system accuracy. However, in such implementations, both resolver sensor and ADC channel unbalances introduce significant errors, particularly in the speed output of the tracking loop. The frequency spectrum of the output error is variable depending on the resolver mechanical velocity. This paper presents the design of an autotuning output filter based on the interpolation of precomputed filters for a DSP-based RDC with a type-II tracking loop. A fourth-order peak and a second-order high-pass filter are designed and tested for an experimental RDC. The experimental results demonstrate significant reduction of the peak-to-peak error in the estimated speed. |
Sponsorship | IEEE Industrial Electronics Society |
Starting Page | 1134 |
Ending Page | 1139 |
Page Count | 6 |
File Size | 1245401 |
File Format | |
ISSN | 02780046 |
Volume Number | 62 |
Issue Number | 2 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2015-01-01 |
Publisher Place | U.S.A. |
Access Restriction | One Nation One Subscription (ONOS) |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | speed control Adaptive filter design ADC imbalances resolver sensor |
Content Type | Text |
Resource Type | Article |
Subject | Control and Systems Engineering Electrical and Electronic Engineering Computer Science Applications |
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