NDLI: DCCS: Double Circular Caching Scheme for DRAM/PRAM Hybrid Cache

Content Provider	IEEE Xplore Digital Library
Author	Jen-Wei Hsieh Yuan-Hung Kuan
Copyright Year	1968
Abstract	DRAM is widely adopted as a cache for secondary storage due to its small access latency. Compared with DRAM, PRAM draws a lot of attention recently, since it provides higher density and has no need to refresh the capacitor charge periodically. The non-volatile nature of PRAM can even reduce compulsory miss, which cannot be avoided by DRAM cache. However, PRAM cache cannot replace DRAM cache due to its endurance issue. Thus DRAM/PRAM hybrid cache becomes a good alternative for traditional DRAM cache. Least recently used (LRU) replacement algorithm and CLOCK-Pro algorithm work well for traditional DRAM cache. But these algorithms shall not be directly applied to DRAM/PRAM hybrid cache since the characteristics of PRAM are not considered. This paper proposed a double circular caching scheme (DCCS) to manage DRAM/PRAM hybrid cache. In our scheme, cached data migrate between DRAM cache and PRAM cache adaptively to achieve good hit ratio while frequent writes to PRAM cache are avoided for endurance concern. The experimental results showed that our scheme can reduce up to 87.10 percent PRAM write accesses for readintensive access pattern and up to 44.90 percent energy consumption for write-intensive access pattern, compared with other caching schemes.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	3115
Ending Page	3127
Page Count	13
File Size	1166472
File Format	PDF
ISSN	00189340
Volume Number	64
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase change random access memory Clocks Computer architecture Algorithm design and analysis Microprocessors Data transfer replacement strategy PRAM hybrid cache
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The cache DRAM architecture: a DRAM with an on-chip cache memory

Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue

A Hybrid PRAM and STT-RAM Cache Architecture for Extending the Lifetime of PRAM Caches

Design of Hybrid Second-Level Caches

CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

Hybrid Main Memory for High Bandwidth Multi-Core System

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Advances in DRAM interfaces

Phase-Change Memory Optimization for Green Cloud with Genetic Algorithm

DCCS: Double Circular Caching Scheme for DRAM/PRAM Hybrid Cache

Similar Documents

The cache DRAM architecture: a DRAM with an on-chip cache memory

Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue

A Hybrid PRAM and STT-RAM Cache Architecture for Extending the Lifetime of PRAM Caches

Design of Hybrid Second-Level Caches

CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

Hybrid Main Memory for High Bandwidth Multi-Core System

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Advances in DRAM interfaces

Phase-Change Memory Optimization for Green Cloud with Genetic Algorithm

DCCS: Double Circular Caching Scheme for DRAM/PRAM Hybrid Cache