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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhong Zheng Zhiying Wang Lipasti, M. |
| Copyright Year | 2002 |
| Abstract | Memory bandwidth is critical to GPGPU performance. Exploiting locality in caches can better utilize memory bandwidth. However, memory requests issued by excessive threads cause cache thrashing and saturate memory bandwidth, degrading performance. In this paper, we propose adaptive cache and concurrency allocation (CCA) to prevent cache thrashing and improve the utilization of bandwidth and computational resources, hence improving performance. According to locality and reuse distance of access patterns in GPGPU program, warps on a stream multiprocessor are dynamically divided into three groups: cached, bypassed, and waiting. The data cache accommodates the footprint of cached warps. Bypassed warps cannot allocate cache lines in the data cache to prevent cache thrashing, but are able to take advantage of available memory bandwidth and computational resource. Waiting warps are de-scheduled. Experimental results show that adaptive CCA can significant improve benchmark performance, with 80 percent harmonic mean IPC improvement over the baseline. |
| Sponsorship | IEEE Computer Society |
| Starting Page | 90 |
| Ending Page | 93 |
| Page Count | 4 |
| File Size | 594802 |
| File Format | |
| ISSN | 15566056 |
| Volume Number | 14 |
| Issue Number | 2 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-07-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Bandwidth Resource management Instruction sets Concurrent computing Benchmark testing Cache memory concurrency GPGPU cache |
| Content Type | Text |
| Resource Type | Article |
| Subject | Hardware and Architecture |
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