NDLI: A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs

Content Provider	IEEE Xplore Digital Library
Author	Abbas, Z. Mastrandrea, A. Olivieri, M.
Copyright Year	1993
Abstract	Logic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We propose a novel logic-level leakage estimation model based on the characterization of voltages at the internal nodes of digital cells, in conjunction with the characterization of leakage currents in a single field-effect transistor (FET) device and with the input-dependent Kirchhoff current law expression of the total current in the cell topology. The voltage-based nature of the approach simplifies the inclusion of supply voltage variation/scaling impact, as well as of output voltage drop (loading effect), on leakage currents. The method has been implemented in hardware description language models of a complete cell library. Exhaustive tests report average accuracy below 1% error in 22-nm CMOS and 20-nm FinFET technologies, when compared with SPICE BSIM simulation results.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	2549
Ending Page	2560
Page Count	12
File Size	2826532
File Format	PDF
ISSN	10638210
Volume Number	22
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Leakage currents Integrated circuit modeling FinFETs Logic gates Voltage control Loading VLSI. Leakage current standard cells VLSI
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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