NDLI: An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme

Content Provider	IEEE Xplore Digital Library
Author	Chun-Chi Chen Shih-Hao Lin Chorng-Sii Hwang
Copyright Year	2004
Abstract	An area-efficient CMOS time-to-digital converter (TDC) based on a pulse-shrinking scheme with an improved cyclic delay line is proposed to achieve low thermal sensitivity in this brief. First, by only thermally compensating the pulse-shrinking unit rather than all delay cells, a large number of compensated circuits could be removed to reduce costs, and the thermal sensitivity of the TDC was still greatly reduced. Additionally, based on the improved cyclic delay line with identical logic gates, an undesired shift resolution caused by the mismatch between the inhomogeneous gates can be successfully eliminated, and the effective resolution can be completely determined by the pulse-shrinking unit. The proposed circuit was fabricated in a Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.35- μm CMOS technology and has an extremely small chip area of 0.025 mm², which is much smaller than the 0.12 mm² of its predecessor. The effective resolution is approximately 40 ps/LSB (least significant bit), and the corresponding integral nonlinearity errors are all within ±0.6 LSB. The experimental results show that a ±5.5% resolution variation of the proposed TDC was achieved in a 0 °C-100 ^°C temperature range. The measured power consumption is 1.65 μW at a measurement rate of 10 samples/s.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	163
Ending Page	167
Page Count	5
File Size	666922
File Format	PDF
ISSN	15497747
Volume Number	61
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Delay lines CMOS integrated circuits Delays Temperature measurement Semiconductor device measurement Sensitivity time-to-digital converter (TDC) Delay line pulse shrinking thermal compensation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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