NDLI: Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture

Content Provider	IEEE Xplore Digital Library
Author	Chen, F.T. Yu-Sheng Chen Tai-Yuan Wu Tzu-Kun Ku
Copyright Year	1980
Abstract	A 3-D resistive random access memory potentially offers lowest cost per bit and highest bit density memory architecture without the use of transistors in the array. However, without the use of selectors attached to each cell in the array, sneak currents are a key concern, causing signal errors, and excess power dissipation. A nonlinear LRS helps to resolve the issue, but to date, reported LRS nonlinearity values are still insufficient. In this letter, we describe how a 1TNR architecture may be designed and operated to take more advantage of the HRS rather than the LRS nonlinearity, allowing sneak currents to be minimized during write operations, without the use of cell selectors. We show how a recently studied TaOx/HfOx device with highly nonlinear ( ~ 10⁵) HRS can be used in block sizes up to 256 Mb without selectors in a 1T8R architecture with a 25% current margin.
Sponsorship	IEEE Electron Devices Society
Starting Page	223
Ending Page	225
Page Count	3
File Size	626233
File Format	PDF
ISSN	07413106
Volume Number	35
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Arrays Resistance Three-dimensional displays Transistors Ash resistive memory RRAM
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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