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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yao-Jen Chang Cheng-Ta Ko Kuan-Neng Chen |
| Copyright Year | 1980 |
| Abstract | A wafer-level 3-D integration scheme using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding was developed and investigated with electrical characterization and reliability assessment. The hybrid bonding could be achieved below 250 °C. Low Kelvin resistance and stable daisy chain resistance were achieved in 5- and 10- μm TSV test structures across the whole wafer. Without obvious deterioration in reliability test results, the integrated Cu TSV and hybrid bond scheme can be potentially designed for 3-D integration applications. |
| Sponsorship | IEEE Electron Devices Society |
| Starting Page | 102 |
| Ending Page | 104 |
| Page Count | 3 |
| File Size | 405264 |
| File Format | |
| ISSN | 07413106 |
| Volume Number | 34 |
| Issue Number | 1 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Bonding Resistance Tin Through-silicon vias Semiconductor device reliability Kelvin 3-D integration Hybrid bonding through-silicon via (TSV) |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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