NDLI: A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

Content Provider	IEEE Xplore Digital Library
Author	Meng-Fan Chang Che-Wei Wu Chia-Cheng Kuo Shin-Jang Shen Sue-Meng Yang Ku-Feng Lin Wen-Chao Shen Ya-Chin King Chorng-Jung Lin Yu-Der Chih
Copyright Year	1966
Abstract	ReRAM is a promising candidate for on-chip low-VDD NVM due to its superior write behavior, particularly for frequent-read-seldom-write applications. Nonetheless, this approach requires a robust and fast low-VDD read scheme. Current-mode sense amplifiers (CSA) are commonly used in NVM; however, they suffer low-yield and degraded speed at a low VDD, due to an insufficient on-off current difference ( I ON-OFF) and the need for large voltage head room (VHR). This study developed a body-drain-driven (BDD) read scheme to suppress VHR and provide resistance-aware dynamic bitline bias voltage for increasing I ON-OFF. The proposed scheme achieved 2.1 × faster read speed, > 1.7× higher yield, and > 2× longer BL length at 0.5 V VDD than conventional CSAs. A fabricated 65 nm 4 Mb ReRAM macro using the proposed read scheme and our logic-compatible ReRAM cell achieved a 45 ns random read access time at VDD=0.5 V. The proposed sensing scheme also achieved a 0.32 V VDDmin.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	2250
Ending Page	2259
Page Count	10
File Size	2627499
File Format	PDF
ISSN	00189200
Volume Number	48
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data structures Boolean functions Sensors Nonvolatile memory Resistance Power demand Transistors sense amplifier ReRAM
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Low ${rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

An embedded ReRAM using a small-offset sense amplifier for low-voltage operations

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

28-nm 2T High-$K$ Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

A 0.13 µm 8 Mb Logic-Based Cu $_{rm x}$Si $_{rm y}$O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

Similar Documents

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Low ${rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

An embedded ReRAM using a small-offset sense amplifier for low-voltage operations

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

28-nm 2T High-$K$ Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

A 0.13 µm 8 Mb Logic-Based Cu $_{rm x}$Si $_{rm y}$O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro