NDLI: Design Optimization of Multigate Bulk MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Ho, B. Xin Sun Changhwan Shin Tsu-Jae King Liu
Copyright Year	1963
Abstract	The design optimization of multigate bulk MOSFET structures is investigated for sub-20-nm gate lengths. Three-dimensional device simulations were used to optimize device design parameters such as the retrograde channel doping profile, as well as the length, width, and height of the gated channel region. Compared with the FinFET design, the results indicate that the tri-gate MOSFET design is promising for continued bulk-Si CMOS transistor scaling, because it can achieve similar on-state current performance and intrinsic delay [for the same channel stripe pitch (SP)] at a lower height/width aspect ratio (0.8 versus 2.17) and less aggressive retrograde channel doping gradient for improved manufacturability. Only by increasing the height of the channel region and/or reducing the channel SP can the FinFET bulk MOSFET design achieve better delay, but at the cost of reduced manufacturability.
Sponsorship	IEEE Electron Devices Society
Starting Page	28
Ending Page	33
Page Count	6
File Size	850036
File Format	PDF
ISSN	00189383
Volume Number	60
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Doping Logic gates Delay Design optimization multigate FET FinFET intrinsic delay MOSFET
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs

Scale-Length Assessment of the Trigate Bulk MOSFET Design

Device Design and Optimization Considerations for Bulk FinFETs

Stack Gate Technique for Dopingless Bulk FinFETs

Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET

Negative Bias Temperature Instability in p-FinFETs With 45 $^{circ}$ Substrate Rotation

First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

Method for Extracting Doping Concentration and Flat-Band Voltage in Junctionless Multigate MOSFETs Using 2-D Electrostatic Effects

Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

Design Optimization of Multigate Bulk MOSFETs

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Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs

Scale-Length Assessment of the Trigate Bulk MOSFET Design

Device Design and Optimization Considerations for Bulk FinFETs

Stack Gate Technique for Dopingless Bulk FinFETs

Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET

Negative Bias Temperature Instability in p-FinFETs With 45 $^{circ}$ Substrate Rotation

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